The present disclosure relates to a high-density semiconductor device, and more particularly to a high-density semiconductor device capable of reducing a time consumed for loading data on a global Input/Output (I/O) line.
In general, the higher the density of a DRAM, the larger the chip size, resulting in the deterioration of DRAM characteristics. Specifically, if the DRAM has at least 8 banks, the length of the global input/output (GIO) line is greatly extended, and the extended GIO line increases the loading time of the GIO line, resulting in the deterioration of address access time (tAA) characteristics.
Typically, in the case of reading data from a DRAM, cell data is selected by a column selection signal, is amplified by a main amplifier, and is then loaded on a global input/output (GIO) line. However, if the GIO line has a long length, a long period of time and a large amount of current signals are consumed to transfer data via the long GIO line, such that read- or write-operation characteristics are unavoidably deteriorated. A representative example of the long GIO line is a 2G DDR2 DRAM, because the 2G DDR2 DRAM including 8 banks must share 8 banks, such that it has the length of about 42000 μm.